The NB3N853501E is a low skew 3.3 V supply 2:1:4 clock distribution fanout buffer. An Input MUX selects one of two LVCMOS/LVTTL CLK lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using LVCMOS/LVTTL levels. A CLK_EN pin can enable or disable the outputs synchronously to eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable outputs, LOW to disable output).

• Four differential LVPECL Outputs
• Operating range: VCC = 3.3 5% V( 3.135 to 3.465 V)
• Two Selectable LVCMOS/LVTTL CLOCK Inputs
• Up to 266 MHz Clock Operation
• Output to Output Skew: 30 ps
• Device to Device Skew 250 ps (Max.)
• Propagation Delay 1.9 ns (Max.)
• Additive Phase Jitter, RMS: 0.023 ps (Typ)
• Industrial Temp. Range (40C to 85C)