The NB3N501 is a clock multiplier that will generate one of nine selectable output multiples of an input frequency via two 3 level select inputs (S0, S1). It accepts a standard fundamental mode crystal or an external reference clock signal. Phase Locked Loop (PLL) design techniques are used to produce a low jitter, TTL level clock output up to 160 MHz with a 50% duty cycle. An Output Enable (OE) pin is provided, and when asserted low, the clock output goes into tri state (high impedance). The NB3N501 is commonly used in electronic systems as a cost efficient replacement for crystal oscillators.

• Clock Output Frequencies up to 160 MHz
• Nine Selectable Multipliers of the Input Frequency
• Operating Range: VDD = 3.3 V +/-10% or 5.0 V +/-5%
• Low Jitter Output of 25 ps One Sigma (rms)
• Zero ppm Clock Multiplication Error
• 45% to 55% Output Duty Cycle
• TTL/CMOS Output with 25 mA TTL Level Drive
• Crystal Reference Input Range of 5 to 27 MHz
• Input Clock Frequency Range of 2 to 50 MHz
• OE, Output Enable with Tri State Output
• 8-Pin SOIC
• Industrial Temperature Range -40 Degrees C to +85 Degrees C