The NB3L8543S is a high performance, low skew 1−to−4 LVDSClock Fanout Buffer.The NB3L8543S features a multiplexed input which can be drivenby either a differential or single−ended input to allow for thedistribution of a lower speed clock along with the high speed systemclock.The CLK_SEL pin will select the differential CLK and CLKb inputswhen LOW (or left open and pulled LOW by the internal pull−downresistor). When CLK_SEL is HIGH, the differential PCLK and PCLKbinputs are selected.The common clock enable pin, CLK_EN, is synchronous so that theoutputs will only be enabled/disabled when they are already in theLOW state. This avoids any chance of generating a runt clock pulse onthe outputs during asynchronous assertion/deassertion of the clockenable pin. The internal flip flop is clocked on the falling edge of theinput clock; therefore, all associated specification limits arereferenced to the negative edge of the clock input.

• Four Differential LVDS Output Pairs
• Two Selectable Differential Clock Inputs
• CLK/CLKb Can Accept LVPECL, LVDS, HCSL, HSTL and SSTL
• PCLK/PCLK Can Accept LVPECL, LVDS, CML and SSTL
• Maximum Output Frequency: 650 MHz
• Additive Phase Jitter, RMS: 50 fs (typical)
• Output Skew: 40 ps (maximum)
• Part−to−part Skew: 200 ps (maximum)
• Propagation Delay: 1.9 ns (maximum)