MC74LCX16373
Low Voltage CMOS 16-Bit Transparent Latch
制造商:ON
产品信息
The MC74LCX16373 is a high performance, non-inverting 16-bit transparent latch operating from a 2.3 to 3.6V supply. The device is byte controlled. Each byte has separate Output Enable and Latch Enable inputs. These control pins can be tied together for full 16-bit operation. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V
specification of 5.5V allows MC74LCX16373 inputs to be safely driven from 5V devices.
The MC74LCX16373 contains 16 D-type latches with 3-state 5V-tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state outputs are controlled by the Output Enable(OEnbar) inputs. When OEbar is LOW, the outputs are enabled. When OEbar is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches.
specification of 5.5V allows MC74LCX16373 inputs to be safely driven from 5V devices.
The MC74LCX16373 contains 16 D-type latches with 3-state 5V-tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state outputs are controlled by the Output Enable(OEnbar) inputs. When OEbar is LOW, the outputs are enabled. When OEbar is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches.
- Designed for 2.3 to 3.6V V
- Operation
- 5.4ns Maximum t
- 5V Tolerant - Interface Capability With 5V TTL Logic
- Supports Live Insertion and Withdrawal
- I
- Specification Guarantees High Impedance When V
- = 0V
- LVTTL Compatible
- LVCMOS Compatible
- 24mA Balanced Output Sink and Source Capability
- Near Zero Static Supply Current in All Three Logic States (20
- A) Substantially Reduces System Power Requirements
- Latchup Performance Exceeds 500mA
- ESD Performance: Human Body Model >2000V; Machine Model >200V
- These are Pb-Free Devices
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