The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops withindividual D inputs and Q outputs. The common buffered Clock (CP) input loadsall flip-flops simultaneously, when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D input, one setup timebefore the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop's Q output. The CE input must be stable only one setup time prior to theLOW-to-HIGH clock transition for predictable operation.

• Ideal for Addressable Register Applications
• Clock Enable for Address and Data Synchronization Applications
• Eight Edge-Triggered D Flip-Flops
• Buffered Common Clock
• Outputs Source/Sink 24 mA
• See MC74AC273 for Master Reset Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• ACT377 Has TTL Compatible Inputs
• Pb-Free Packages are Available