MC10EP57
1 Differential, ECL, 3.3 V / 5.0 V
制造商:ON
产品信息
The MC10/100EP57 is a fully differential 4:1 multiplexer. By leaving the SEL1 line open (pulled LOW via the input pulldown resistors) the device can also be used as a differential 2:1 multiplexer with SEL0 input selecting between D0 and D1. The fully differential architecture of the EP57 makes it ideal for use in low skew applications such as clock distribution.
The SEL1 is the most significant select line. The binary number applied to the select inputs will select the same numbered data input (i.e., 00 selects D0).
Multiple V
outputs are provided. The V
pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
as a switching reference voltage. V
may also rebias AC coupled inputs. When used, decouple V
and V
via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, V
should be left open.
The 100 Series contains temperature compensation.
The SEL1 is the most significant select line. The binary number applied to the select inputs will select the same numbered data input (i.e., 00 selects D0).
Multiple V
outputs are provided. The V
pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
as a switching reference voltage. V
may also rebias AC coupled inputs. When used, decouple V
and V
via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, V
should be left open.
The 100 Series contains temperature compensation.
- 375 ps Typical Propagation Delays
- Maximum Frequency > 2 GHz Typical
- PECL Mode Operating Range: V
- = 3.0 V to 5.5 V with V
- = 0 V
- NECL Mode Operating Range: V
- = 0 V with V
- = -3.0 V to -5.5 V
- Open Input Default State
- Safety Clamp on Inputs
- Q Output will default LOW with inputs open or at V
- V
- Outputs
- Useful as Either 4:1 or 2:1 Multiplexer
- These are Pb-Free Devices
电路图、引脚图和封装图
技术资料
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