The MC10EP/100EP52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to V
) the outputs of the device will remain stable.

• 330ps Typical Propagation Delay
• Maximum Frequency > 4 GHz Typical
• PECL Mode: V
• = 3.0 V to 5.5 V with V
• = 0 V
• NECL Mode: V
• = 0 V with V
• = -3.0 V to -5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Q Output will default LOW with inputs open or at V
• Pb-Free Packages are Available