MC10E431
ECL 3-Bit Differential Flip-Flop
制造商：ON
产品信息
The MC10E/100E431 is a 3-bit flip-flop with differential clock, data input and data output.
The asynchronous Set and Reset controls are edge-triggered rather than level controlled. This allows the user to rapidly set or reset the flip-flop and then continue clocking at the next clock edge, without the necessity of de-asserting the set/reset signal (as would be the case with a level controlled set/reset).
The E431 is also designed with larger internal swings, an approach intended to minimize the time spent crossing the threshold region and thus reduce the metastability susceptibility window.
The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the Dbar and the CLKbar sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5 V below V
.
The 100 Series contains temperature compensation.
The V
pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
as a switching reference voltage. V
may also rebias AC coupled inputs. When used, decouple V
and V
via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
should be left open.
The asynchronous Set and Reset controls are edge-triggered rather than level controlled. This allows the user to rapidly set or reset the flip-flop and then continue clocking at the next clock edge, without the necessity of de-asserting the set/reset signal (as would be the case with a level controlled set/reset).
The E431 is also designed with larger internal swings, an approach intended to minimize the time spent crossing the threshold region and thus reduce the metastability susceptibility window.
The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the Dbar and the CLKbar sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5 V below V
.
The 100 Series contains temperature compensation.
The V
pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
as a switching reference voltage. V
may also rebias AC coupled inputs. When used, decouple V
and V
via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
should be left open.
- Edge-Triggered Asynchronous Set and Reset
- Differential D, CLK and Q; V
- Reference Available
- 1100MHz Min. Toggle Frequency
- PECL Mode Operating Range: V
- = 4.2 V to 5.7 V with V
- = 0 V
- NECL Mode Operating Range: V
- = 0 V with V
- = -4.2 V to -5.7 V
- Internal Input Pulldown Resistors
- ESD Protection: > 1 kV HBM, > 75 V MM
- Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
- Moisture Sensitivity Level 1
- For Additional Information, see Application Note AND8003/D
- Flammability Rating: UL-94 code V-0 @ 1/8",Oxygen Index 28 to 34
- Transistor Count = 348 devices
- Pb-Free Packages are Available
电路图、引脚图和封装图
MC10E431电路图