MC100LVEP14

5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer

制造商:ON

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产品信息

The MC100LVEP14 is a low skew 1 to 5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions.
  • 100 ps Device-to-Device Skew
  • 25 ps Within Device Skew
  • 400 ps Typical Propagation Delay
  • Maximum Frequency > 2 GHz Typical
  • PECL and HSTL Mode: V
  • = 2.375 V to 3.8 V with V
  • = 0 V
  • NECL Mode: V
  • = 0 V with V
  • = -2.375 V to -3.8 V
  • LVDS Input Compatible
  • Open Input Default State

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    MC100LVEP14电路图

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    技术资料

    应用案例