The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applications which require the ultimate in AC performance at 3.3V V
.
The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the LVEL51 allow the device to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to V
and the CLKbar input will be biased at V
/2.

• 475ps Propagation Delay
• 2.8GHz Toggle Frequency
• ESD Protection: >4 KV HBM, >200 V MM
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V
• = 3.0 V to 3.8 V with V
• = 0 V
• NECL Mode Operating Range: V
• = 0 V with V
• = -3.0 V to -3.8 V
• Internal Input Pulldown Resistors
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
• For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
• Transistor Count = 114 devices
• Pb-Free Packages are Available