The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal.
The V
output allows the EPT21 to be cap coupled in either single-ended or differential input mode. When single-ended cap coupled, V
output tied to the D0 input for a non-inverting buffer or the D0 input for an inverting buffer. When cap coupled differentially, V
output is connected through a resistor to each input pin. If used, the V
pin should be bypassed to V
via a 0.01 F capacitor. For additional information see AND8020. For a single-ended direct connection use an external voltage reference source such as a resistor divider. Do not use V
for a single-ended direct connection.

• 1.4ns Typical Propagation Delay
• Maximum Frequency > 275 MHz Typical
• 24mA TTL outputs
• LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
• The 100 Series Contains Temperature Compensation
• V
• Output
• New Differential Input Common Mode Range