元器件型号、描述、参数

MC100EP35

 ECL JK Flip-Flop

制造商：ON

中文资料及数据手册

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产品信息

The MC10EP35 is a higher speed/low voltage version of the EL35 JK flip flop. The JK data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.
The 100 Series contains temperature compensation.
  • 410 ps Propagation Delay
  • Maximum Frequency > 3 GHz Typical
  • PECL Mode Operatio Range: V
  • = 3.0 V to 5.5 V with V
  • = 0 V
  • NECL Mode Operating Range:V
  • = 0 V with V
  • = -3.0V to -5.5V
  • Open Input Default State
  • Q Output will default LOW with inputs open or at V
  • Pb-Free Packages are Available

电路图、引脚图和封装图

    MC100EP35电路图

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    技术资料

    应用案例