MC100EP16VC

 Differential Driver / Receiver with High Gain and Enable Output

制造商:ON

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产品信息

The EP16VC is a world-class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain and enable output.
The EP16VC provides an ENbar input which is synchronized with the data input (D) signal in a way that provides litchless gating of the Q
and Q
bar outputs.
When the ENbar signal is LOW, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and ENbar goes HIGH, it will force the Q
LOW and the Q
bar HIGH on the next negative transition of the data input. If the data input is LOW when the ENbar goes HIGH, the next data transition to a HIGH is ignored and Q
remains LOW and Q
bar remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The Q
and Q
bar outputs remain in their disabled state as long as the ENbar input is held HIGH or LOW. The ENbar input has no influence on the Qbar output and the data input is passed on (inverted) to this output whether ENbar is HIGH or LOW. This configuration is ideal for crystal oscillator applications where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output.
The V
pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
as a switching reference voltage. V
may also rebias AC coupled inputs. When used, decouple V
and V
via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
should be left open.
The 100 Series contains temperature compensation.
  • 310 ps Typical Prop Delay Qbar, 380 ps Typical Prop Delay QHG, QHGbar
  • Gain > 200
  • Maximum Frequency > 3 GHz Typical
  • PECL Mode Operating Range: V
  • = 3.0 V to 5.5 V with V
  • = 0 V
  • NECL Mode Operating Range: V
  • = 0 V with V
  • = –3.0 V to –5.5 V
  • Open Input Default State
  • Q
  • Output Will Default LOW with D inputs Open or at V
  • V
  • Output

电路图、引脚图和封装图

    MC100EP16VC电路图

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    技术资料

    应用案例