The MC100EP016A is a high-speed synchronous, presettable, cascadeable 8-bit binarycounter. Architecture and operation are the same as the MC100E016 in the ECLinPS family.
The counter features internal feedback to TCbar gated by the TCLD (Terminal Count Load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the TCbar feedback is disabled, and counting proceeds continuously, with TCbar going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated.
COUT and COUTbar provide differential outputs from a single, non-cascaded counter or divider application. COUT and COUTbar should not be used in cascade configuration. Only TCbar should be used for a counter or divider cascade chain output.
A differential clock input has also been added to improve performance.
The 100 Series contains temperature compensation.

• 550 ps Typical Propagation Delay
• Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016
• PECL Mode Operating Range:V
• = 3.0 V to 3.6 V with V
• = 0 V
• NECL Mode Operating Range: V
• = 0 V with V
• = -3.0 V to -3.6 V
• Open Input Default State
• Safety Clamp on Clock Inputs
• Internal TCbar Feedback (Gated)
• Addition of COUT and COUTbar
• 8-bit
• Differential Clock Input
• V
• Output
• Fully Synchronous Counting and TCbar Generation
• Asynchronous Master Reset
• Pb-Free Packages are Available