CM2009
VGA Port Companion Circuit
制造商：ON
产品信息
The CM2009 connects between a video graphics controller embedded in a PC, graphics adapter card or set top box and the VGA or DVI-I port connector. The CM2009 incorporates ESD protection for all signals, level shifting for the DDC signals and buffering for the SYNC signals. ESD protection for the video, DDC and SYNC lines is implemented with low-capacitance current steering diodes. All ESD diodes are designed to safely handle the high current spikes specified by IEC-61000-4-2 Level 4 (±8KV contact discharge if C
is present, ±4KV if not). The ESD protection for the DDC signal pins are designed to prevent ''back current'' when the device is powered down while connected to a monitor that is powered up. Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage video controller ICs to provide design flexibility in multi-supply-voltage environments. Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the video controller IC (SYNC1,SYNC2). These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and V
, which is typically 5V. Additionally, each driver has a series termination resistor (R
) connected to the SYNC_OUT pin, eliminating the external termination resistors typically required for the HSYNC and VSYNC lines of the video cable. There are three versions with different values of RT to allow termination at typically 65Ω (CM2009-00) or 15Ω (CM2009-02). The 15Ω(CM2009-02) version will typically require two external resistors which can be chosen to exactly match the characteristic impedance of the SYNC lines of the video cable. Two N-channel MOSFETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage than the monitor. The gate terminals for these MOSFETS (V
) should be connected to the supply rail
is present, ±4KV if not). The ESD protection for the DDC signal pins are designed to prevent ''back current'' when the device is powered down while connected to a monitor that is powered up. Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage video controller ICs to provide design flexibility in multi-supply-voltage environments. Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the video controller IC (SYNC1,SYNC2). These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and V
, which is typically 5V. Additionally, each driver has a series termination resistor (R
) connected to the SYNC_OUT pin, eliminating the external termination resistors typically required for the HSYNC and VSYNC lines of the video cable. There are three versions with different values of RT to allow termination at typically 65Ω (CM2009-00) or 15Ω (CM2009-02). The 15Ω(CM2009-02) version will typically require two external resistors which can be chosen to exactly match the characteristic impedance of the SYNC lines of the video cable. Two N-channel MOSFETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage than the monitor. The gate terminals for these MOSFETS (V
) should be connected to the supply rail
- Includes ESD protection, level-shifting, buffering and sync impedance matching
- 7 channels of ESD protection for all VGA port connector pins meeting IEC-61000-4-2 Level 4 ESD requirements (±8kV contact discharge)
- Very low loading capacitance from ESD protection diodes on VIDEO lines, 4pF maximum
- Bi-directional level shifting N-channel FETs provided for DDC_CLK & DDC_DATA channels
- 5V drivers for HSYNC and VSYNC lines