74LVC573
Low Voltage CMOS Octal Transparent Latch Flow Through Pinout
制造商:ON
产品信息
The 74LVC573A is a high performance, non-inverting octal transparent latch operating from a 1.2 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V
specification of 5.5V allows 74LVC573A inputs to be safely driven from 5V devices.
The 74LVC573A contains 8 D-type latches with 3-state standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state standard outputs are controlled by the Output Enable (OEbar) input. When OEbar is LOW, the standard outputs are enabled. When OEbar is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches. The 74LVC573A flow through design facilitates easy PC board layout.
specification of 5.5V allows 74LVC573A inputs to be safely driven from 5V devices.
The 74LVC573A contains 8 D-type latches with 3-state standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state standard outputs are controlled by the Output Enable (OEbar) input. When OEbar is LOW, the standard outputs are enabled. When OEbar is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches. The 74LVC573A flow through design facilitates easy PC board layout.
- Designed for 1.2 to 3.6 V V
- Operation
- 5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic
- Supports Live Insertion and Withdrawal
- I
- Specification Guarantees High Impedance When V
- = 0 V
- 24 mA Output Sink and Source Capability
- Near Zero Static Supply Current in All Three Logic States (10 µA) Substantially Reduces System Power Requirements
- Latch-up Performance Exceeds 250 mA
- ESD Performance: Human Body Model >2000 V; Machine Model >200 V
- These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant
在线购买
型号:74LVC573ADTR2G
描述:-
应用案例
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